1. Field of the Invention
The present invention relates to processor address buses, and more particularly to an apparatus and method for quad-pumped/double-pumped address bus which solves the problem of large package and unreasonable power requirements for a present day microprocessor where a significant amount of pins and power are devoted to the microprocessor's address bus interface.
2. Description of the Related Art
In a present day microprocessor, such as an x86-compatible microprocessor, transactions (i.e., read and write transactions) to/from memory are accomplished over a system bus. These transactions include a request phase where an address for a transaction along with the transaction type are provided over an address signal group. The address signal group typically includes an address bus, a set of corresponding address strobe signals, and a request bus. In one particular conventional configuration, the address signal group includes about 40 or so signals which must be provided on pins of a package for the microprocessor die. Many conventional configurations double-pumped multiple bus request packets (e.g., “A” and “B” request packets) on the address signal group during a single clock cycle. And further, many conventional microprocessor configurations support “quad-pumped” transactions in which an entire cache line (e.g., eight quadwords for a 64-byte cache line) is transferred across the bus in just a few clock cycles (e.g., two clock cycles). In the conventional double-pumped transactions, the signals of the address signal group are asserted twice during each clock cycle.
The present inventor has noted that this address signal group configuration is problematic in certain application areas where package size and/or power are constrained. Furthermore, every time one of these signals is driven to the bus, such as multiple assertions in a given clock cycle, additional power is consumed. It is therefore desirable to provide a mechanism whereby the number of address signal group pins and commensurate power requirements are reduced, but where the addressing functionality is retained. Furthermore, to accommodate varying application areas, it is desirable to provide a mechanism whereby an addressing capability can be configured in either a double-pumped mode as described above or in a new quad-pumped mode, as will be described herein.